1. Field of the Invention
The present invention relates generally to the synchronization of multiple circuits or integrated circuit chips. In particular, the present invention relates to an apparatus and method for ensuring that multiple circuits or chips generate system clocks that are in phase with one another.
2. Related Art
A problem often arises when multiple circuits, or chips, or combinations thereof, are coupled together as a synchronized system, but are each driven by their own phase locked loop (PLL). If each circuit or chip requires the PLL output frequency to be divided down to a lower frequency to generate its operating (i.e., system) clock frequency, then the possibility exists that, after a reset, and the individual PLLs each acquire lock, the circuits or chips could start operating with clocks that are out of phase with each other. This problem may exist even when the PLLs of the individual circuits or chips are driven by the same input oscillator source.
The above-referenced problem is illustrated in greater detail with reference to FIGS. 1 and 2.
A system 10 comprising two chips 12A, 12B, each containing a PLL 14A, 14B, is illustrated in FIG. 1. Each PLL 14A, 14B, is driven by a 30 MHz input clock signal 16 produced by a 30 MHz oscillator (not shown), and is configured to provide an output frequency of 120 MHz . If each chip 12A, 12B, has a required operating frequency (i.e., system clock) of 40 MHz , the output clock signal 18A, 18B, of each PLL 14A, 14B, must be divided by a factor of three in order to generate a system clock signal 20A, 20B, having the desired clock frequency. In this example, a divide-by-three circuit 22A, 22B, is provided in each chip 12A, 12B, to furnish the necessary frequency division.
After a reset signal 24 is provided to the PLLs 14A, 14B, each PLL 14A, 14B, will take some period of time to become locked. A typical system, e.g., system 10, uses this lock indication to begin propagating the system clock signal 20A, 20B, to the internal logic of the chips 12A, 12B. Since both PLLs 14A, 14B, are driven by a common input clock signal 16, the output clock signals 18A, 18B of the PLLs 14A, 14B, once locked, are guaranteed to be in phase. However, since the example system 10 includes a divide-by-three circuit 22A, 22B, on the output of each PLL 14A, 14B, the exact startup time of each divide-by-three circuit 22A, 22B, will affect the phase relationship of the resultant system clock signals 20A, 20B. The timing diagram shown in FIG. 2 illustrates how, if each PLL 14A, 14B, becomes locked at a slightly different time, the resultant system clock signals 20A, 20B, will be out of phase.
To compound this problem, some PLL configurations, based on the amount of jitter present on the input clock signal, may momentarily lose lock even though continuing to produce acceptable output clock signals. This causes the interruption of system clock generation for those systems that use the locked indicator as a gating condition. Further, it is also possible that one or more PLLs in the system do not achieve lock at all.
A need therefore exists for a solution which addresses both the problem of synchronization of multiple circuits or chips, as well as the problem of momentary (or permanent) deactivation of the PLL locked indication.
The present invention provides an apparatus and method for synchronizing multiple circuits or chips clocked at a divided phase lock loop (PLL) frequency.
Generally, the present invention provides an apparatus comprising:
a plurality of chips, each chip including a phase locked loop (PLL) and a circuit for generating a system clock signal;
a circuit for receiving the lock signal from each PLL and for generating an All-Locked signal in response to all of the PLLs achieving lock; and
a synchronizing circuit for synchronizing the system clocks of the plurality of chips upon receipt of the All-Locked signal
In addition, the present invention provides a method comprising:
providing a plurality of chips, each chip including a phase locked loop (PLL) and a circuit for generating a system clock signal;
generating an All-Locked signal in response to all of the PLLs achieving lock; and
synchronizing the system clock signals of the plurality of chips in response to receipt of the All-Locked signal, wherein the system clock signals are in phase.
The foregoing and other features of the invention will be apparent from the following more particular description of the invention.